Yoon Seok Yang

Dr. Yang is a SW/HW engineer and computer scientist at Intel in Hillsboro, Oregon. His research interests
​include SW/HW co-design for mobile platforms, system-on-chip, network-on-chip, multiprocessor architecture,
​DSP, image processing, and security. He has the PhD degree in electrical and computer engineering from
​Texas A&M University, College Station. He is a member of IEEE.


• Design, development, and verification of SoCs for mobile systems
• SW skills: C/C++/Perl
• RTL design skills:  SystemC/VHDL/Verilog/ASIC/FPGA
• Debugging/troubleshooting SW and HW
• Major in VLSI design, computer architecture, DSP, network-on-chip (NoC), image processing, cryptograph
• Research in channel-source decoding systems and parallel processing on network-on-chips


RTL design, VLSI design, DSP, system-on-chip, embedded system, interconnect and router design for network-on-chip, video compression and decompression algorithm (MPEG2, MPEG4, H.264), joint source coding, LDPC decoder, MIMO detector, processor design, computer architecture, cryptography(encryption/decryption processor), HW and SW co-design


​Hardware Engineer at Intel, Hillsboro, OR, Aug. 2012 ~ Current
Intel Architecture Group (IAG)
• Pre-Silicon SW development group focused on the development of co-emulation/co-simulation platforms for next generation phone/tablets

Ph.D. in Computer Engineering, Texas A&M, Aug. 2008 ~ Aug. 2012
Research/Teaching assistant Jan. 2009 ~ Aug. 2012
Low latency and energy efficient router design for network-on-chips (NoCs)
• Developed routers for low latency NoCs and error correction codes (ECCs) for low power NoCs
Research on low power joint decoding systems including H.264 video decoder, LDPC channel decoder, and MIMO detector
• Developed a joint source coding model using H.264 decoder, LDPC decoder, and MIMO detector
Digital signal processing units for sensor network systems
• Data compression for radiation detection

Graduate Intern at Intel Labs, Hillsboro, OR. June 2011 ~ Nov. 2011 (5.5 months)
DSP accelerator design
• Developed DSP accelerator supporting configurable MAC, FFT, FIR, and 3-D cross product operations for embedded SoC processors
• Implemented the DSP accelerator on XILINX Virtex-6 FPGA ML605 board

Graduate ​Intern at Intel Labs, Hillsboro, OR. May 2009 ~ Aug. 2009 (3.5 months)
Delivered 802.3 NIC drivers having the ability to split network packet header and data and transfer them into different memory space for DirectPath
• Worked on the driver and application level enabled a key feature of DirectPath, i.e. the ability for the
network device to DMA into two different places including one in the application space.
Developed IOSF Traffic Generator (TG) RTL components
• Worked on IOSF blocks which is a critical milestone of Intel On-die Switch Fabric (IOSF) Traffic Generator

​Graduate Intern at Broadcom Corporation, Irvine, CA. Jan. 2007 ~ Dec. 2007 (1 year)
Worked at Mobile Platform Group
Researched hardware abstract layer (HAL) for power management unit on 3G WCDMA and HSDPA platform
Researched power control scheme for mobile platform
Developed device drivers for 3G mobile phones

​Graduate Intern at Morpho Technology. June 2006 ~ Sep. 2006 (3.5 months)
Worked at ASIC group for developing WiMAX SoCs
​Designed hardware IPs programmed in Verilog and VHDL
Verified and evaluated the IPs on FPGA board

​M.S. in Computer Engineering, UC Irvine, Sep. 2005 ~ Mar. 2008
Research in execution unit and security block design for NoCs
• Researched multi-processor system-on-chips (MPSoCs) and NoCs
• Researched 32-bit RISC processing elements for NoCs
• Researched cryptograph algorithms for NoCs
• Designed an NoC platform composed of routers and RISC processors programmed in Verilog, VHDL and SystemC
• Development of encryption/decryption engines for NoCs

​Senior Research Engineer at LG Digital TV Lab, Korea, Feb. 2000 ~ June 2005
Digital Multimedia Broadcasting (DMB) SoC Projects 
DMB-I, DMB-II SoC Projects
• Developed the world first DMB SoCs
• Researched and developed SoCs for DMB mobile phones
• Developed hardware IPs of IRDETO conditional access system (CAS) for satellite DMB
• Researched the architecture of DSP for multimedia processing using configurable and extensible 32-bit Tensilica Xtensa processor for DMB SoCs
• Implemented hardware MPEG2 / MPEG4 system decoders for DMB SoCs
• Developed personal video recorder (PVR) systems to store multimedia data on a flash memory
• Verified SoCs using Quick-Turn Emulator and FPGA Board, and evaluated in real-time DMB systems
• Programmed firmware for DMB SoCs
DTV (Digital TV) SoC Projects
TPN, TPN-II, OOB, OOB-II, HD-I, HD-II, Heron SoC Projects
• Researched DTV SoCs and developed transport de-multiplexers (ATSC,DVB, DIRECTV, Open-Cable, ARIB), video decoders, video display processors
• Developed all security blocks and CAS used in LG DTVs
Implemented SoCs for security such as AES (DIRECTV, PVR), DES (DIRECTV, Open-Cable), MULTI2 (ARIB), DVB- CS (NDS, IRDETO) scramblers and descramblers
• Developed a PVR system for DTV embedding 120G HDD
• Integrated overall IPs such as ARM core, system, video, and audio decoders into a single DTV SoC
• Used real-time OS (Wind River VX-WORKS)


Texas A&M University, College Station, USA
PhD, ECE, Aug. 2008 ~ Aug. 2012
• Research in router and interconnect architecture for NoC and MPSoC
• Research in joint channel-source coding and ASIC designs for communication, multimedia, and DSP IPs

University of California, Irvine, USA
MS, EECS, Mar. 2008
• Courses related: NoC, MPSoC, cryptography, DSP, VLSI Design, parallel processing, computer architecture, digital system

Hanyang University, Korea
MS, control and instrumentation engineering (now ECE), Feb. 2000
• Courses related: cryptography, computer architecture, VLSI Design, DSP, parallel processing, and image processing
BS, control and instrumentation engineering (now ECE), Feb. 1998


• TL2005 (Technology Leadership 2005) Gold Award, LG DTV lab, Feb. 2003
• Superior Idea Award, LG DTV lab, Aug. 2001
• Outstanding Research Engineer Award, LG DTV lab, Jan. 2001